Manufacturers of microelectronic devices are continually reducing the size and increasing the density of components in integrated circuits to (a) increase the speed and capacity of a device and (b) reduce power consumption. For example, to increase the capacity of a memory device, such as an SRAM device, it is highly desirable to reduce the size of each memory cell without impairing performance. Memory device manufacturers accordingly seek to reduce the size and/or increase the density of components in memory cells.
As integrated circuits are scaled down, it becomes more difficult to fabricate the individual components, which increases the cost of fabricating integrated circuits. For example, as memory cells in SRAM devices shrink, several micro-fabrication processes require extensive development to form such small structures with the necessary precision and repeatability for production level processing. The equipment and procedures for producing ever smaller components accordingly becomes more expensive.
One process that may become a limiting factor for producing the small components in high performance devices is photolithography. As a result, every masking step dramatically increases the cost of manufacturing a given device. A typical damascene gate structure, for example, requires three or more deposition and planarizing steps. Photolithography (i.e., pattern/etch) is thus an expensive aspect of forming damascene gate structures and interconnects in memory devices, processors and other devices. As a result, there is a continuing need for structures and manufacturing methods to form damascene gates and interconnects with a high degree of consistency and reliability.